This invention generally relates to BCH decoders and methods for decoding BCH encoded blocks of data. More specifically, the present invention relates to such decoders which utilize microprocessor based circuits to implement decoding algorithms.
Transmitted data are often encoded using error correcting codes to maximize a probability of a data receiver obtaining precisely the data that a data transmitter intends to transmit. One desirable class of codes which may be used for such error correction are known as Bose-Chaudhuri-Hocquenghem (BCH) codes. A transmitter must encode the data in a predetermined manner which will be known to those skilled in the art once a particular BCH code has been selected. The encoded data is then transmitted and received by a receiver. The receiver must then decode the BCH encoded data and correct any indicated errors before it obtains the data that the transmitter intended to transmit.
Decoding BCH encoded data is a relatively complicated task compared to encoding BCH data. Prior art BCH decoders tent to utilize a large quantity of special purpose linear feedback logic circuits to perform the steps required by BCH decoding algorithms. Such special purpose circuits permit the decoder to rapidly decode BCH encoded data, but result in a relatively expensive, less reliable, and inflexible decoder. On the other hand, microprocessor based circuits are capable of simply and inexpensively performing the algorithms required by a BCH decoder. However, a straight forward simulation of the linear feedbacks circuits conventionally used in BCH decoders results in a BCH decoder which performs the decoding task too slowly to be of value in many applications.